With the advance of semiconductor technology, impact of interconnection routing on performance parameters such as electro-migration (EM), parasitic resistances and capacitors (parasitic RC), and voltage drop (IR drop), become more and more severe in advanced node, such as 14 nm and 10 nm nodes, IC designs. It takes designers an undesirable amount of design time in verification and fixing.
FIG. 1 is a simplified conventional design flow 100 of an IC. At 102 the design schematic is entered and simulations are performed. At 104 the design layout is formed. After multiple iterations and following the completion of the layout and sign-off at 106, the design is taped out at 108. During the layout phase 104, the impact of various electrical parameters are unknown to designers until the layout is finished and passed into sign-off checks. But it is often too difficult at such a late stage to fix the electrical impacts. Designers might need to re-design the layout from very beginning and they may need several such iterations to make a design clean of errors. This leads to a long turn-around-time. A need for an efficient and user-friendly verification flow to prevent the electrical-impact verifications from being the bottle-neck of layout designs continues to exist.